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Meta, Tianke Heda, Mu De Weina, how to cross over silicon carbide AR glasses         With the rapid development of augmented reality (AR) technology, smart glasses, as an important carrier of AR technology, are gradually moving from concept to reality. However, the popularity of smart glasses still faces many technical challenges, especially in terms of display technology, weight, heat dissipation and optical performance. In recent years, silicon carbide (SiC) as an emerging material, with its excellent physical and optical properties, has been widely used in a variety of power semiconductor devices and modules, and now it has also become a key material in the field of AR glasses across the border. The high refractive index, excellent heat dissipation performance and high hardness of silicon carbide make it show great application potential in the display technology, lightweight and heat dissipation of AR glasses. The following will discuss how silicon carbide brings revolutionary changes to smart glasses from the aspects of silicon carbide characteristics, technological breakthroughs, market applications and future prospects.       Characteristics and advantages of silicon carbide     Silicon carbide is a kind of wide band gap semiconductor material with high hardness, high thermal conductivity and high refractive index. These properties give it a wide range of potential applications in electronic devices, optical devices and thermal management. Specific to the field of smart glasses, the advantages of silicon carbide are mainly reflected in the following aspects:   The first is the high refractive index: the refractive index of silicon carbide is as high as 2.6 or more, much higher than that of traditional glasses materials such as resin (1.51-1.74) and glass (1.5-1.9). The high refractive index means that silicon carbide can more effectively constrain light propagation and reduce light energy loss, thereby improving display brightness and field of view (FOV). For example, Meta's Orion AR glasses use silicon carbide waveguide technology to achieve a 70-degree field of view, far exceeding the 40 degrees of traditional glass materials.   It is excellent heat dissipation performance: the thermal conductivity of silicon carbide is hundreds of times that of ordinary glass, and it can conduct heat quickly. For AR glasses, heat dissipation is a key issue, especially in high brightness displays and long periods of use. Silicon carbide lenses can quickly conduct the heat of the optical machine, thereby improving the stability and service life of the equipment.   High hardness and wear resistance: silicon carbide is one of the hardest materials known, its hardness is second only to diamond. This makes the silicon carbide lenses more wear-resistant and suitable for everyday use. In contrast, glass and resin materials are easy to scratch, affecting the user experience.         Fourth, anti-rainbow effect: traditional glass materials are easy to produce rainbow effect in AR glasses, that is, the dynamic color light pattern formed after the reflection of ambient light on the waveguide surface. By optimizing the grating structure, silicon carbide can effectively eliminate the rainbow effect easily produced by traditional glass materials in AR glasses, that is, the dynamic color light pattern formed by the reflection of ambient light on the waveguide surface, thereby improving the display quality.       Technological breakthrough of silicon carbide in AR glasses     In recent years, the technological breakthrough of silicon carbide in the field of AR glasses is mainly reflected in the research and development of diffractive optical waveguide lenses. Diffracted optical waveguide is a display technology based on the diffraction phenomenon of light and the combination of waveguide structure, which can propagate the image generated by the optical machine through the grating in the lens, thereby reducing the lens thickness and making the appearance of AR glasses more similar to ordinary glasses.     In October 2024, Meta (formerly Facebook) used a combination of silicon carbide etched waveguides + microleds in its AR glasses Orion, solving key bottlenecks in field of view, weight and optical artifacts for AR glasses. Pascual Rivera, a Meta optics scientist, said that silicon carbide waveguide technology has revolutionized the display quality of AR glasses, transforming them from a "disco like rainbow spot of light" to a "symphony hall like quiet experience."   In December 2024, Shuoke Crystal successfully developed the world's first 12-inch high-purity semi-insulated silicon carbide single crystal substrate, marking a major breakthrough in the field of silicon carbide materials in the field of large-size substrates. This technology will accelerate the expansion of silicon carbide in new applications such as AR glasses and heat sink. For example, a 12-inch silicon carbide wafer can be made into 8-9 pairs of AR glasses lenses, significantly increasing production efficiency.         Recently, silicon carbide substrate supplier Tianke Heda and micro nano optoelectronic device company Mode Micro Nano jointly established a joint venture company to focus on the development and marketing of AR diffraction optical waveguide lens technology. Tianke Heda, with its technology accumulation in the field of silicon carbide substrates, will provide high-quality silicon carbide substrate products to Munde, while Munde will leverage its advantages in micro-nano optical technology and AR optical waveguide processing to further optimize the performance of diffractive optical waveguides. This collaboration is expected to accelerate technological breakthroughs in AR glasses and drive the industry towards higher performance and lighter weight.   The second generation of silicon carbide AR glasses exhibited by Mode Weina at SPIE AR|VR|MR 2025 weigh only 2.7 grams per lens, the thickness is as thin as 0.55 mm, which is even thinner than the daily wear sunglasses, so that users can hardly feel its existence when wearing, truly "light pack".         Jingsheng Electromechanical also recently said that it is actively promoting industry technological innovation and domestic replacement of the whole industrial chain equipment, as these enterprises accelerate the expansion of production capacity, China is expected to significantly alleviate the global semi-insulated silicon carbide substrate supply and demand contradictions in the next three years. This will help push the optical limits and enable silicon carbide to enable AI+AR applications.       Application case of silicon carbide in AR glasses       In the manufacturing process of silicon carbide waveguide, the Meta team overcame the technical problem of slope etching. Nihar Mohanty, research manager, said bevel etching is a non-traditional grating technique that distributes etched lines at oblique angles to optimize the efficiency of light coupling in and out.   This technological breakthrough has laid the foundation for the large-scale application of silicon carbide in AR glasses. Meta's Orion AR glasses are representative applications of silicon carbide technology in the AR field. By using silicon carbide waveguide technology, Orion achieves a 70-degree field of view Angle and effectively solves problems such as double shadows and rainbow effects.         Giuseppe Carafiore, head of AR waveguide technology at Meta, notes that silicon carbide's high refractive index and thermal conductivity make it an ideal material for AR glasses.   After the material was identified, the next hurdle turned to the fabrication of waveguides - specifically, an unconventional grating technique called bevel etching. "The grating is the nanostructure responsible for coupling light into and out of the lens," explains Carafiore. "For the silicon carbide to work, the grating must be etched with a bevel. The etched lines are not arranged vertically, but at an oblique Angle."   Nihar Mohanty added that they are the first team in the world to achieve slope etching directly on the device, and the entire industry has relied on nanoimprint technology in the past, but this cannot be applied to high refractive index substrates. For this reason, no one had considered the silicon carbide option before.   In 2019, Nihar Mohanty and his team partners jointly built an exclusive production line, before which most semiconductor chip suppliers and foundries lacked relevant equipment because slope etching technology was not yet mature. Therefore, at that time, there was no facility in the world that could produce etched silicon carbide waveguides, and it was impossible to verify the technical feasibility outside the laboratory. Nihar Mohanty further revealed that it was a significant investment and they built the complete production chain. The processing equipment was customized by the partners and the process was developed by Meta itself - initially the equipment was only up to research grade standards because there was no manufacturing grade system at the time, so they then worked with the manufacturing partners to develop the production grade bevel etching equipment and process.   Now that the potential of silicon carbide has been proven, the Meta team is looking forward to the rest of the industry starting to develop their own devices, because the more companies invest in optical grade silicon carbide research and development and equipment development, the more robust the industry ecosystem for consumer AR glasses will be.       Challenges and future prospects of silicon carbide     Although silicon carbide shows great potential in AR glasses, its application still faces some challenges. At present, the price of silicon carbide materials is high, mainly due to its slow growth rate and difficult processing. For example, Meta's Orion AR glasses lenses cost up to $1,000 per lens, which is difficult to meet the needs of the consumer market.   However, with the rapid development of the new energy automobile industry, the cost of silicon carbide is gradually decreasing. In addition, the development of large-size substrates (such as 12 inches) will further drive cost reduction and efficiency. The high hardness of silicon carbide makes it very difficult to process, especially in the micro and nano structure processing, the yield is low.   In the future, with the deep cooperation between silicon carbide substrate manufacturers and micro and nano optical manufacturers, this problem is expected to be solved. The application of silicon carbide in AR glasses is still at an early stage, and more enterprises need to participate in the research and development of optical grade silicon carbide and equipment development. The Meta team is looking forward to other manufacturers in the industry to invest in relevant research and jointly promote the industrial ecological construction of consumer AR glasses.       ZMSH 12inch SiC substrate 4H-N type           * Please contact us for any copyright concerns, and we will promptly address them.          

AR silicon carbide waveguide analysis, from the perspective of waveguide design       01     Breakthroughs in materials often bring an industry to new heights and even open up new scientific and technological space for mankind.   The birth of silicon launched the entire era of semiconductors and computing, becoming the basis for silicon-based life.   So, will the emergence of silicon carbide bring AR waveguides to new heights?   Let's first look at the design of the waveguide.     Only by understanding the requirements at the system level can we clarify the direction of material optimization.   The most classic architecture of AR waveguides comes from the former Hololens Dr. Tapani Levola of Finland, and the waveguides are divided into three regions: the entry pupil region, the dilated pupil region, and the exit pupil region.   AR waveguide this piece, the Finns are the absolute core driving force.     From the earliest Nokia, to the Hololens, to the later Dispelix and so on.         (Tapani's classic patent for AR diffracted waveguide, filed at Nokia in 2002, is 23 years old)         02     The entry pupil region of the waveguide couples the entire FOV from the optical machine through the grating into the substrate, which can be glass, silicon carbide material, or even resin material.   Its working principle is similar to optical fiber transmission, when the incidence Angle meets the condition of total reflection, the light will be bound in the base and transmitted to the pupil enlargement area through total reflection.   In the dilated pupil region, light is replicated in the X direction and continues to the exit pupil region.   In the exit pupil region, light is copied in the Y direction and eventually coupled out to the human eye.   If the exit pupil of the optical machine (that is, the entry pupil of the waveguide) is compared to a "round cake", then the essence of the AR waveguide is to copy this "cake" from the optical machine into multiple, such as 4x4, in the exit pupil region.   Ideally, these "cakes" are expected to overlap each other to form a smooth, uniform brightness and color surface, so that the user sees the same picture anywhere on this surface (high uniformity).         AR waveguide design must first consider the requirements of FOV, which determines the size of the picture the user sees, and also affects the design requirements of the optical machine.   The second is the requirements of the Eyebox, which determines whether the user can see the full picture within the eye movement range, affecting comfort.   Finally, there are other indicators, such as brightness uniformity, color uniformity and MTF.   Summarize the flow of AR waveguide design:     Determine the FOV and Eyebox, select the waveguide architecture, set optimization variables and objective functions, and then make continuous optimization adjustments.   So, what does this have to do with silicon carbide? It matters.     The most important diagram in waveguide design is the k-vector wave vector diagram.     In simple terms, incident light (at a specific wavelength and Angle) can be represented as a vector.   The square box in the center represents the FOV size of the incident picture, and the ring area represents the FOV range that the waveguide material of that refractive index can support, beyond which light cannot exist in the waveguide.         The higher the refractive index of the base material, the larger the circle of the outermost ring, and the larger the FOV that can be supported.   Each time the grating is touched, an additional vector is superimposed on the incoming light. The magnitude of the superimposed vector of the grating is related to the wavelength of the incident light.   Therefore, light of different colors coupled into the grating will jump to different positions in the ring (inside the waveguide) due to different raster vectors.   Therefore, a single chip to achieve RGB three colors, can support a lot less FOV than monochrome.       03     To achieve large FOV, there is not only one way to increase the refractive index of the base, there are at least two ways to choose.   For example, it can be done through the splicing of FOV, such as the Hololens classic Butterfly architecture.   The grating in the input region cuts the incident FOV in half, transmits it from the left and right sides to the dilated pupil region, and splice it in the exit pupil region.   In this way, even with low refractive index materials, large FOV can be achieved.     With this architecture, Hololens 2 achieves FOV of more than 50 degrees based on a glass substrate with a refractive index of less than 1.8.     (FOV Spliced waveguide Classic patent filed by Microsoft Hololens2 in 2016)       It is also possible to achieve very large FOV through some architectural design of two-dimensional raster, which involves many details and is inconvenient to expand.   From the FOV point of view, the higher the refractive index of the base, the higher the upper limit of the system.   From this point of view, silicon carbide does provide a higher ceiling for the system.   As a waveguide designer, I certainly like silicon carbide because it gives me enough freedom to design.   But from the user's perspective, it doesn't really matter what base to use.     As long as it can meet the demand, good performance, low price, and light machine, it is a good choice.   Therefore, the choice of silicon carbide or other substrates should be considered comprehensively by the product team.   Need to be considered according to the application scenario, price positioning, design specifications, industrial chain maturity and other aspects.       04     To summarize:     1. If purely from the perspective of FOV, the current high refractive index glass achieves FOV of 50 degrees without pressure.   2. but if you want to achieve more than 60 degrees of FOV, silicon carbide is indeed a good choice.   Materials are a choice at the component and architecture level, and architecture in turn serves the function of the system, and ultimately through the product, to serve the user.     This is a tradeoff process, we need to choose from multiple dimensions such as scene experience, product form, system architecture, components and materials.       ZMSH SIC Substrate 4H/6H-N/Semi/3C/4H/6H-P Type Display             * Please contact us for any copyright concerns, and we will promptly address them.      

Meta: Why did we choose SiC?     On March 6, Meta (formerly Facebook) published an article on its official website, describing the process and advantages of choosing silicon carbide as the core material when developing AR glasses waveguide technology.   The Meta team has not only solved key bottlenecks such as field of view, weight and optical artifacts of AR glasses through silicon carbide waveguide technology, but also sees it as a "game changer" in the AR industry, which may become a mainstream material in the future:       Meta Orion team explains: Why choose SiC technology       In 2019, the Orion team prepared Meta founder and CEO Mark Zuckerberg for a pivotal demonstration of the potential waveguide technology for augmented reality glasses - the moment when theoretical calculations on paper became reality for the first time and revolutionized the trajectory of subsequent development.     Meta released AR glasses -Orion     Pascual Rivera, a Meta-optics scientist, recalls: "When wearing glasses with glass base waveguides and multiple laminated panels, it felt like being in a disco - there were rainbow spots everywhere, and the interference was so strong that it was impossible to see the AR content. But when you put on the prototype glasses with silicon carbide waveguides, it is instantly like being in a symphony Hall listening to a quiet classical movement, and your attention is always focused on the complete experience we have built. It's a total game changer."   However, while the choice of silicon carbide as a substrate may seem obvious today, it was far from a given when the Meta Orion team embarked on the development of AR glasses a decade ago:   Pascual Rivera explained that silicon carbide is often heavily doped with nitrogen, which makes it appear green, or even black if it is thick enough. Such a material simply cannot be used to make optical lens-it is essentially electronic, and its color is closely related to its electronic properties.   Giuseppe Calafiore, head of waveguide technology at Meta AR, adds that silicon carbide has a long history as an applied material, mainly in high-power electronics. Take electric cars for example: All electric cars require a chip that can withstand extremely high power to drive the wheels and complete vehicle systems. Traditional silicon substrates cannot meet this demand, and only materials such as silicon carbide that allow high current and high power through can be competent.   Before the renewable energy issue heated up in recent years, the market for such high-power chips was far smaller than for consumer electronics chips. In addition, the long-term price of silicon carbide is high, but due to the small amount of substrate for automotive chips, the cost is still acceptable, and manufacturers lack the motivation to reduce prices.   But it turns out that silicon carbide also has key properties required for waveguides and optics, and the parameter the Meta Orion team is most focused on is the refractive index. The high refractive index of silicon carbide means that it can conduct and output huge amounts of optical data - an analogy to Internet bandwidth: the greater the bandwidth, the more data can be transmitted within the channel. Optics follow the same logic: the higher the refractive index of a material, the greater its optical expansion, and the greater the amount of optical data transmitted through that channel.   Calafiore further explained that in our application scenario, the channel is the waveguide, and the greater optical expansion directly translates into a wider field of view. The higher the refractive index of the material, the larger the field of view that the display can support.       SiC refractive index up to 2.7: far more than glass, lithium niobate and other materials       When Calafiore first joined Oculus Research (Meta's research and development lab) in 2016, the highest refractive index glass they had was only 1.8 - multiple layers of glass had to be stacked to achieve the target field of view. Optical artifacts aside, the assembly process is extremely complex: the first two waveguides must be perfectly aligned, and then the entire stack must be perfectly matched to the third waveguide.   "Not only is this expensive, but it's also obvious that there's no way you can fit three pieces of glass into each lens." Calafiore recalled, "They were too heavy, and the thickness was far beyond the limit of aesthetics - no one would buy such products. So we went back to square one: trying to increase the refractive index of the substrate material, thereby reducing the number of glass plates required."   In the beginning, the research team first focused on lithium niobate, which has a refractive index of about 2.3, significantly higher than glass's 1.8.   Calafiore said that we realized that we could just stack two boards, or maybe even cover the field of view with one board. At the same time, we began to explore other materials - which is why we found excellent transparency in high-purity silicon carbide in our work with suppliers in 2019. More importantly, the refractive index of silicon carbide is as high as 2.7, setting a record for optical applications.         For the research team, this value means that the refractive index of silicon carbide is 17.4% higher than that of lithium niobate and 50% higher than that of glass. Calafiore explained, "It is possible to prepare transparent silicon carbide with only a small modification of existing industrial equipment. So we adjusted the process to strictly control the parameters - no longer optimizing for electronic properties, but focusing on optical properties: core metrics such as transmittance and refractive index uniformity."       Solving problems such as ghosting and rainbow effect: SiC technology finally stands out     At the time, the Reality Labs team was the first to attempt to convert opaque silicon carbide wafers into transparent substrates. Because silicon carbide is one of the hardest materials known, its cutting and polishing must rely on diamond tools, which leads to extremely high costs of non-repetitive engineering and ultimately expensive substrates.     Although there are more cost-effective alternatives to silicon carbide substrates, there are advantages and disadvantages to any technology, and Meta ultimately decided to go with silicon carbide. Silverstein, scientific director of Meta Research, explained that finding the ideal solution for wide-field AR displays is essentially a game of performance versus cost, which may be compressed, but if performance is not up to par, the cost advantage is meaningless.   At the same time, the Meta Orion's field of view is up to 70 degrees, and new problems such as gghost and rainbow effect begin to appear: gghost is a repeat image of the main image projected on the display, and rainbow effect is a dynamic color pattern formed by the reflection of ambient light on the waveguide surface.   For example, Silverstein explains, if you're driving at night and the headlights move around you like rainbow stripes, or playing volleyball on a sunny beach, the dynamic rainbow effect can cause you to miss your shot. One of the magical properties of silicon carbide is that it can completely eliminate these disturbances. Another unique advantage of silicon carbide is its thermal conductivity. Plastics are poor insulators, as are glass and lithium niobate, but silicon carbide is both transparent as glass and efficient at conducting heat - defying conventional wisdom.   Therefore, in July 2020, the Meta Orion team selected silicon carbide based on three core factors:         First, shape optimization: single-layer substrate and smaller support structure greatly reduce the volume of equipment;   Second, optical advantages: high refractive index and anti-rainbow effect improve the display quality;   The third is lightweight: compared with the double glass scheme, the weight is significantly reduced.       Meta solves the problem of slope etching: We hope that more enterprises will participate in the research and development of optical grade SiC     After the material was identified, the next hurdle turned to the fabrication of waveguides - specifically, an unconventional grating technique called bevel etching.   Calafiore explained, "The grating is the nanostructure responsible for coupling light into and out of the lens, and for the silicon carbide to work, the grating must be etched with a bevel. The etched lines are not arranged vertically, but are distributed at an oblique Angle.   Nihal Mohanty, research manager at Meta, added that they are the first team in the world to achieve slope etching directly on the device, and the entire industry has relied on nanoimprint technology in the past, but this cannot be applied to high refractive index substrates. For this reason, no one had considered the silicon carbide option before.   In 2019, Nihar Mohanty and his team partners jointly built an exclusive production line, before which, because the slope etching technology is not mature, most semiconductor chip suppliers and foundries lack relevant equipment. Therefore, at that time, there was no facility in the world that could produce etched silicon carbide waveguides, and it was impossible to verify the technical feasibility outside the laboratory.   Nihal Mohanty further revealed that it was a major investment and they built the complete production chain. The processing equipment was customized by the partners and the process was developed by Meta itself - initially the equipment was only up to research grade standards because there was no manufacturing grade system at the time, so they then worked with the manufacturing partners to develop the production grade bevel etching equipment and process.   Now that the potential of silicon carbide has been proven, the Meta team is looking forward to the rest of the industry starting to develop their own devices, because the more companies invest in optical grade silicon carbide research and development and equipment development, the more robust the industry ecosystem for consumer AR glasses will be.       SiC cost reduction and efficiency path is clear: it will shine in the field of AR glasses       While the Meta team is still exploring alternatives, a strong consensus has emerged: in the right market window, the right people are working together to drive the silicon carbon-based AR glasses revolution.   Silverstein and Giuseppe Calafiore said that prior to this, all silicon carbide manufacturers had significantly expanded production in preparation for the expected electric vehicle boom, and the current overcapacity situation did not exist when Orion was in development. Now, because of oversupply, the cost of the substrate has begun to fall.   The Orion project proved the viability of silicon carbide in AR glasses, and there is now strong interest from supply chains across three continents, with suppliers excited about new opportunities to manufacture optically grade silicon carbide. After all, compared to electronic chips, each waveguide lens consumes a larger amount of material, and their existing technical capabilities can be seamlessly transferred to this field, they are betting on this opportunity, silicon carbide will eventually win.   In addition, there are already manufacturers shifting from 6-inch to 8-inch substrates, and there are pioneer companies developing cutting-edge technologies for 12-inch substrates - which will make AR glasses production capacity increase exponentially. In the future, these developments will continue to drive costs downward, and while the industry is still in its early stages, the picture of the future is becoming clearer.   Calafiore believes that at the beginning of any new technological revolution, people will always try multiple paths, and television technology is an example: from the cathode ray tube to the LED plasma screen, and now MicroLED, we have gone through multiple iterations of the technology architecture. Most of the paths in the exploration are eventually falsified, but there are always a few options that are repeatedly chosen because of their great potential. We have not yet reached the end, nor can we fight alone, but silicon carbide is undoubtedly a miracle material worthy of heavy investment.   Silverstein concluded that they have successfully demonstrated the crossover potential of silicon carbide in electronics and photonics, and its future may shine in areas such as quantum computing. At the same time, the possibility of significantly reducing the cost of silicon carbide has appeared, although there are still many challenges, but its revolutionary energy is immeasurable.       ZMSH SIC Wafer 4H-N & Semi Type:             * Please contact us for any copyright concerns, and we will promptly address them.          

Connection between wafer flat and notch   Wafer flat and notch are important features used to determine wafer orientation during wafer manufacturing, and they play a crucial role in wafer processing, alignment and inspection.   1. Wafer Flat   Wafer flat refers to the flat part of the outer edge of the wafer, which is used to mark the specific direction of the wafer and ensure that the wafer can be correctly aligned during the processing and disposing of the wafer. Think of it as a compass pointer that helps guide the correct placement of wafers in the device.     Function and Effect:   Direction indication: The positioning edge usually shows the specific crystal face orientation of the wafer. For example, for a P-type silicon wafer, the positioning edge can help to indicate its main orientation. This is because silicon crystal structures with different crystal orientations differ in physical and electrical properties, and the role of the wafer positioning edge is to ensure that the crystal orientation is correctly identified during wafer processing.   Alignment mark: In wafer manufacturing, it is necessary to perform multiple step alignment operations, such as lithographic alignment, etching alignment, etc. The positioning edge is like a coordinate identifier on a map to help the device align the wafer position and ensure processing accuracy.   Example analogy: The positioning edge of a wafer can be compared to the indicator lines in a jigsaw puzzle, telling us how to correctly assemble the various parts. Without these lines, we might not be able to complete the puzzle correctly.   2. Wafer Notch   A wafer notch is a small cut or notch in the outer edge of a wafer. This groove is similar to the positioning edge and also has the role of marking the direction of the wafer, but its shape and function are different. Typically, the notch is a physical notch, while the positioning edge is flat.     Function and Effect:   Precise positioning: Notch is often used to provide more accurate directional identification, especially in larger wafers such as 300mm wafers. Through the notch, manufacturing equipment is able to more easily identify the orientation of the wafer, avoiding alignment errors due to rotation or slight movement of the wafer.   Avoid alignment errors: The notches serve as markers that help the automation equipment more stably keep the wafer oriented throughout the process. It reduces human error and increases productivity.   Example analogy: You can compare the notch to the valve position of a car tire, although it does not affect the rotation of the tire, but it is a key point of positioning the tire to ensure that the tire can be accurately installed.   3. Connection between wafer flat and notch   Wafer flats and notches are complementary to each other during wafer fabrication. The flats provide a general orientation indication for the wafer, while the notches provide a physical marker for further precise positioning. Both are present in most applications, especially in large wafers (such as 300mm wafers).     Collaborative role in wafer processing:   The flat helps determine the general orientation of the wafer and ensures the initial alignment of the wafer; The notch further provides a physical feature that helps the device identify orientation more precisely, ensuring accuracy throughout the manufacturing process.   4. Points for attention in practical applications   Impact during production: The precision of the flat and notch is critical to the machining accuracy of the entire wafer. If there is an error in the positioning of these features, it may cause the electrical characteristics of the entire wafer to be unstable, affecting the performance of the final chip. Therefore, in the production process, it is very important to ensure the accuracy of these features.   Differences in marking methods: Different wafer suppliers may use different marking methods, for example, some wafers may only have flat and no notch; Some may add notch to the flat. When designing these marks, the compatibility of the equipment and the requirements of the production process must be considered.   5. Conclusion   Wafer flats and notches are different in appearance, but together they play an important role in marking wafer orientation and ensuring alignment accuracy. The flat is similar to a compass, helping us determine the general direction. The notch is a more precise physical feature, helping to ensure consistency of direction during manufacturing. These two are indispensable features in modern wafer manufacturing, especially in the production of large-size wafers, playing a more critical role.     ZMSH related products:     Thanks for watching!

Collector of colored gemstones, royal origins of sapphires   Since the beginning of this year, the once lukewarm colored gemstone market has quietly appeared to rise against the trend. New consumer demand has fueled the hot colored gemstone market. And the volume and price have risen. According to the China Treasure Association's market research shows that in the first half of 2023, the average price increase of the whole category of colored gems in China ranges from 30%-50%, and the price increase of large carat or relatively rare gems is as high as 100%-150%.     If you want to collect colored gems, we recommend sapphire as your first choice.   Sapphire and ruby, emerald, diamond are known as the four precious gemstones. With a Mohs hardness of 9, sapphire and ruby are two of the hardest and wear-resistant natural minerals in the world after diamond (Mohs hardness of 10). Sapphire has the color of the sky, symbolizing holiness, tranquility and wisdom, being loved and protected by the gods. Clear dark blue sapphire is the most precious. Since 800 BC, it has been regarded as a precious stone. In the Middle Ages, it was prescribed only for religious clergy, royal and noble jewelry decoration. Inherent holiness and nobility is an important reason why it is sought after by the upper class.     Napoleon, emperor of the First French Empire, fell in love with Josephine, who was six years older than him, at the age of 27. He did not have much money at the time, but he bought a simple but classic design ring for Josephine, announcing their engagement.   Napoleon and Josephine with their engagement ring Designed by Marley Etienne Nidot, founder of Chammet Paris Jewellery   The ring, called "Toi et Moi," which means "you and me" in French, consists of a water drop cut sapphire and a water drop cut diamond, two stones of the same weight and opposite directions, set on a plain gold ring holder. This double gemstone ring symbolizes two people deeply intertwined, full of sincere and profound love. In 1804, Napoleon was crowned Emperor of France, Josephine became the empress of the first French Empire, and this ring also added a touch of "coronation of love" legend.   In the 19th century, Britain's Queen Victoria and Prince Albert were very much in love, and Prince Albert took design inspiration from the family crest and customized a small sapphire and diamond crown for Queen Victoria.   from Victoria and Albert Museum, London   Among the Queen's many gorgeous jewelry sets, this little tiara is not the most luxurious, but it has always been the Queen's favorite. Prince Albert died after 21 years of marriage. Queen Victoria was devastated, and for the next 40 years on the throne, she almost no longer wore other colored jewelry, only wearing this little crown to public events many times, to express the deep love and memory of Prince Albert.     In the 20th century, it was necessary to mention this world-famous Car-tier cheetah brooch. The cheetah brooch, designed by jeweller Car-tier and commissioned by the Duchess of Windsor, features a sapphire-studded, diamond-encrusted 152.35-carat Kashmiri round egg face sapphire. Jeanne Toussaint, Cartier's designer at the time, pioneered the use of cheetah elements to reflect the fearless temperament of women, and since then the cheetah has become a unique symbol of Cartier.     Under the wave of self-liberation of Western women in the early 20th century, women saw their own shadow from it: brave, free, elegant, independent spirit.   For most jewelry lovers, sapphire is a high-quality investment collection balanced with daily wear properties of the gem, suitable for daily wear. This point greatly increases the practicality of precious jewelry.   The color of sapphire varies from very light blue to deep blue, like the pure sky, but also like the quiet sea, the same is they are all calm and elegant. Its luster belongs to the sub-diamond luster in gemology, and it will be found after wearing that it will not shine like the diamond luster, but it is stronger than the glass product luster, bright and not flamboyant.   Sapphire has the industry recognized high-quality origin, Kashmir, Madagascar, Myanmar, Sri Lanka are producing top-quality sapphire, is the preferred origin of businesses and consumers. But Kashmir produced sapphire value is the highest, currently due to territorial disputes, production depletion and mining difficulties and other issues have almost stopped production.   The most famous colors in sapphires are the romantic velvety texture of "Cornflower Blue", and the saturation of high blue or purplish tones of "Royal Blue". Sapphires rated in these two colors are rare in production, high in value, and highly collectible, with high-quality Kashmir cornflower sapphires being extremely rare. In 2014, the "Kashmir Imperial Sapphire", a deep corncar blue that caused a sensation at the auction house, weighed 17.16 carats and eventually set a world auction record for the unit price of sapphire carats at that time at $236,404 per carat, for a total price of $4.06 million. Cornflower Blue Royal Blue   The application of sapphire is very wide, whether it is wedding, banquet, workplace business occasions, are very appropriate. In addition to the most mainstream blue sapphire, there are a variety of colored sapphire to choose from. Sapphire in a broad sense is a general term for all colors of gem-grade corundum except red, such as yellow sapphire, pink sapphire, purple sapphire, pink orange Papalacha sapphire and so on.     In ancient Persian Ferdowsi's epic poem, the vast sky is the reflection of sapphire. How would you choose this gem, once the exclusive preserve of the royal family?     ZMSH Related Products   Thanks for watching!

Detailed version of the silicon wafer semiconductor manufacturing process   1. POLY SILICON STACKING   First, the polysilicon and dopant are put into a quartz crucible in a monocrystalline furnace, and the temperature is raised to more than 1000 degrees Celsius to obtain the molten polysilicon.       2. INGOT GROWING   Ingot growth is a process in which polycrystalline silicon is made into monocrystalline silicon, and after the polysilicon is heated into a liquid, the thermal environment is precisely controlled to grow into high-quality monocrystal.       Related concepts:   Single crystal growth: After the temperature of the polycrystalline silicon solution is stabilized, the seed crystal is slowly lowered into the silicon melt (the seed crystal will also be melted in the silicon melt), and then the seed crystal is lifted upward at a certain speed for the crystallization process. Subsequently, the dislocations generated during the crystallization process are eliminated by necking operation. When necking to a sufficient length, the monocrystalline silicon diameter is increased to the target value by adjusting the drawing speed and temperature, and then the equal diameter is maintained to the target length. Finally, in order to prevent the dislocation and back-delay, the monocrystalline ingot is finished to obtain the finished monocrystalline ingot, which is taken out after the temperature is cooled.   Methods for preparing monocrystalline silicon: Straight-pull method (CZ method) and zone melting method (FZ method). The Straight-pull method is referred to as CZ method, which is characterized by the aggregation of a straight cylinder type thermal system, heated with graphite resistance, and the polycrystalline silicon installed in a high-purity quartz crucible is melted, and then the seed crystal is inserted into the melt surface for welding, and the seed crystal is rotated at the same time, and then the crucible is reversed, and the seed crystal is slowly lifted upward, and the monocrystalline silicon is obtained through the process of crystal introduction, amplification, shoulder turning, equal diameter growth, and finishing.   The zone melting method is a method of using polycrystalline ingots to melt and grow crystalline semiconductor crystals, using heat energy to generate a melting zone at one end of the semiconductor bar, and then welding single crystal seed crystals. The temperature is adjusted so that the molten zone slowly moves towards the other end of the rod, and through the whole bar, it grows into a single crystal with the same direction as the seed crystal. There are two types of zone melting methods: horizontal zone melting method and vertical suspension zone melting method. The former is mainly used for the purification and single crystal growth of germanium, GaAs and other materials. In the latter, a high-frequency coil is used to create a molten zone at the contact between the single crystal seed crystal and the polycrystalline silicon rod suspended above it in an atmosphere or vacuum furnace chamber, and then the molten zone is moved upward for single crystal growth.   About 85% of the wafers are produced by the Zorgial method and 15% by the zone melting method. According to the application, the monocrystalline silicon grown by the Zyopull method is mainly used for the production of integrated circuit components, while the monocrystalline silicon grown by the zone melting method is mainly used for power semiconductors. The Straight-pull process is mature, and it is easier to grow large-diameter monocrystalline silicon; The melt of the zone melting method is not in contact with the container, is not easy to pollute, and has high purity, which is suitable for the production of high-power electronic devices, but it is difficult to grow large-diameter monocrystalline silicon, which is generally only used for a diameter of 8 inches or less. In the video, it is the straight pull method.   3. INGOT GRINDING&CROPPING     Because it is difficult to control the diameter of the monocrystalline silicon rod in the process of pulling the monocrystal, in order to obtain the standard diameter of the silicon rod, such as 6 inches, 8 inches, 12 inches, etc. After pulling the single crystal, the diameter of the silicon ingot will be tumbled, and the surface of the silicon rod after tumbling is smooth, and the dimensional error is smaller.   4. WIRE SAWING     Using advanced wire cutting technology, the single crystal rod is cut into silicon wafers of appropriate thickness through slicing equipment.   5. EDGE GRINDING   Due to the small thickness of the silicon wafer, the edge of the cut silicon wafer is very sharp, and the purpose of edging is to form a smooth edge, and it is not easy to break in the future chip manufacturing.       6. LAPPING   LAPPING is when the chip is added between the heavy selected plate and the lower plate, and the pressure is applied to rotate the chip with the abrasive agent to flatten the chip.     7. ETCHING   Etching is a process that removes processing damage on the surface of a wafer by dissolving the surface layer that has been damaged by physical processing with a chemical solution.     8. DOUBLE SIDE GRINDING   Double-sided grinding is a process that flattens the wafer by removing small bumps on the surface.     9. RAPID THERMAL PROCESS   RTP is a process of rapidly heating the wafer in a few seconds, so that the defects inside the wafer are uniform, inhibit metal impurities, and prevent abnormal semiconductor operation.       10. POLISHING   Polishing is a process that ensures surface evenness through surface precision machining. The use of polishing paste and polishing cloth, with appropriate temperature, pressure and rotation speed, can eliminate the mechanical damage layer left by the previous process, and obtain a silicon wafer with excellent surface flatness.     11. CLEANING   The purpose of cleaning is to remove the residual organic matter, particles, metals, etc. on the surface of the silicon wafer after polishing, so as to ensure the cleanliness of the surface of the silicon wafer and make it meet the quality requirements of the following process.     12. INSPECTION   Flatness & resistivity tester tests the polished silicon wafers to ensure that the thickness, flatness, local flatness, curvature, warpage, resistivity, etc. of the polished silicon wafers meet customer requirements.     13. PARTICLE COUNTING   PARTICLE COUNTING is a process of accurately checking chip surfaces to determine the number of surface defects and defects through laser scattering.     14. EPI GROWING   EPI GROWING is a process of growing high quality silicon single crystal films on a ground silicon wafer by vapor chemical deposition.     Related concepts: Epitaxial growth: refers to the growth of a single crystal layer on the single crystal substrate (substrate) that has certain requirements and is the same as the substrate crystal, as if the original crystal extends outward for a period. Epitaxial growth technology was developed in the late 1950s and early 1960s. At that time, in order to manufacture high-frequency high-power devices, it is necessary to reduce the series resistance of the collector, and require the material to withstand high voltage and high current, so it is necessary to grow a thin high-resistance epitaxial layer on the low resistance substrate. The epitaxial growth of the new single crystal layer can be different from the substrate in terms of conduction type, resistivity, etc., and can also grow multi-layer single crystals with different thicknesses and different requirements, thus greatly improving the flexibility of device design and device performance.   15. PACKING   Packaging is the packaging of the final qualified product.     ZMSH Related Products：  

Warlink Kona ----- Germanium to silicon nitride mid-infrared integrated photonics waveguides   Introduction   A germanium platform with large core-cladding index contrast, silicon nitride germanium waveguide, was demonstrated at mid-infrared wavelength. The feasibility of this structure is verified by simulation. This structure is achieved by first bonding germanium-on-silicon donor wafers deposited with silicon nitride to silicon substrate wafers, and then obtaining the germanium-on-silicon nitride structure by layer transfer method, which is scalable to all wafer sizes.   Introduce   Silicon-based photonics has received a lot of attention in recent years due to its compatibility with CMOS processes and its potential for integration with microelectronics. Researchers have been trying to extend the operating wavelength of photonics to the mid-infrared (MIR), defined here as 2-15 μm, because there are promising applications in MIR, such as next-generation communications, biochemical sensing, environmental monitoring, and more. Silicon on standard insulators (SOI) are not suitable for MIR because the material loss for burying oxide layers becomes very high at 3.7lm and above. Many efforts have been made to find an alternative material system that could work on Mir. Silicon on Sapphire (SOS) waveguide technology has been pursued to extend the operating wavelength range to 4.4lm. Silicon nitride (SON) waveguides, which provide a wide transparency range of 1.2-6.7 μm, have also been proposed. Germanium (ge) has wide transparency and many optical properties, making it a good alternative to SOI.   Germanium on Insulator (GOI) has been proposed, and passive waveguides and active germanium modulators have been manufactured on the platform, but as mentioned above, burying oxide layers actually limits the transparency of the platform. Germanium on SOI has also been reported to have electrical advantages. The germanium on Silicon (GOS) platform is currently widely used in photonics research and has already achieved a number of impressive achievements. The lowest propagation loss germanium waveguide on this platform is only reported to have a loss of 0.6dB/cm. However, germanium (n. 4. The refractive index is 3.8 μm. Therefore, the bending radius of the GOS must be correspondingly greater than the bending radius of the SOI, resulting in the coverage area of the devices on the GOS chip usually greater than the SOI. What is needed is a better alternative germanium waveguide platform that will provide greater core cladding refractive index contrast than GOS, as well as useful transparency and a smaller channel bending radius.   In order to achieve these goals, the structure proposed and implemented in this work is germanium nitride on silicon, here called GON. The refractive index of our PECVD silicon nitride (SiNx) was measured by ellipsometry at 3.8lm. The transparency of SiNx is usually up to about 7.5 mm. So the exponential contrast in GON is. Once this Ge platform operating in the MIR range is implemented, there will be many passive photonic devices that can be manufactured with a compact footprint, such as MachZehnder interferometers, microring resonators, and so on. In order to make a compact ring, a small bending radius is required, which is only possible in high-contrast waveguides with strong optical limitations. Moving forward, compact sensing devices can also be realized based on microring resonators with such germanium platforms. Most importantly, we have developed a viable and scalable wafer bonding and layer transfer technology to implement GON.   Experiment   Germanium/silicon platforms can be manufactured through several technologies. These techniques include germanium condensation, liquid phase epitaxy, 20, and layer transfer techniques.21 However, when germanium is grown directly on silicon nitride, the quality of germanium crystals is expected to be poor and a high density of defects is formed     Graph. 2. Compared with GOS, the simulated bending loss of Nepal government is lower, indicating that the waveguide bending loss of Nepal government is lower.   Because SiNx is amorphous. As a result, these defects increase scattering losses. In this work, we utilize wafer bonding and layer transfer techniques to fabricate GON as shown in Figure 2. Silicon donor wafers use reduced pressure chemical vapor deposition (RPCVD) and a three-step germanium growth process.22 The germanium epitaxial layer is then coated with silicon nitride and transferred to another silicon substrate to obtain GON wafers. For comparison, some germanium silicon (GOS) chips (which grow in a similar way but do not transfer) were included in subsequent experiments. The final germanium layer usually has a penetration dislocation density (TDD) of < 5106cm2, surface roughness < 1nm, and tensile strain of 0.2%.23 In addition, the donor wafer is cleaned to obtain a surface free of oxides and contaminants, then rinsed with deionized water (DI water) and N2 drying. After the cleaning process, the donor wafers are loaded into the Cello PECVD system for the deposition of tension strain SiNx. Annealing for a few hours after deposition ensures that gases trapped in the wafer are released during deposition.   All heat treatments are performed at temperatures below 40 ° C. In addition, another 1 mm SiNx is deposited on the back of the wafer to compensate for the bending effect. By low temperature plasma chemical vapor deposition, the binding layer of 300 nm is finally deposited. The bonding layer is silica, making it easy to bond with another silicon-treated wafer. Due to the use of hydrophilic bonding in this work, water molecules are formed in the bonding reaction. Therefore, silica was chosen as the bonding layer because it can absorb these water molecules, thus providing a high bonding quality.24 The bonding layer is chemically mechanically polished (chemo-mechanical polished) to 100 nm to reduce the surface roughness and make it suitable for wafer bonding. The donor wafer can then be bonded to a silicon substrate wafer. Prior to bonding, both wafer surfaces are exposed to O2 plasma for about 15s to improve surface hydrophilicity.   After that, the Adi washing step is added to increase the density of the surface hydroxyl group, thereby triggering the binding. The bonded wafer pairs are then annealed for about 4 hours after bonding at temperatures below 30 ° C to improve bonding strength. Bonding wafers are examined using infrared imaging to check for interfacial void formation. To complete the layer transfer process, the top silicon donor wafer is ground in order to transfer the germanium/silicon nitride layer stack on the substrate wafer. This is followed by wet etching using tetramethylammonium hydroxide (TMAH) to completely remove the silicon donor wafer. Considering the high selectivity of silicon to germanium, the etching stop occurs at the original germanium/silicon interface.   The germanium/silicon interface layer is then removed by chemical and mechanical polishing. Our process uses two silicon wafers, silicon donor wafers and silicon substrate wafers, so it is scalable to all chip sizes. X-ray diffraction (XRD) analysis was used to characterize the quality of germanium thin films, referring to GOS after the manufacture of Gunn chips, and the results are shown in Figure 4. XRD analysis shows that the crystal quality of Germanium epitaxial layer has no obvious change, and its peak strength and curve shape are similar to that of Germanium on silicon wafer.     Graph. 4. XRD pattern of Geng and GOS germanium epitaxial layer.   Sum up   In summary, defective layers containing mismatched dislocations can be exposed by layer transfer and removed by chemical-mechanical polishing, thus providing a high-quality germanium layer on SiNx under the coating. Simulations were performed to investigate the feasibility of the GON platform providing a smaller channel bend radius. Waveguides are manufactured on GON wafers and characterized at 3.8lm wavelengths. The bending loss at a GON with a radius of 5 mm is 0.1460.01 dB/bend and the propagation loss is 3.3560.5 dB/cm. These losses are expected to be further reduced by using advanced processes (such as electron beam lithography and deep reactive ion etching) or by not structuring to improve sidewall quality.        

Diamond/Copper composite material, break the limit!   With the continuous miniaturization, integration, and high performance of modern electronic devices, including computing, 5G/6G, batteries, and power electronics, the increasing power density leads to severe joule heat and high temperatures in the device channels. This is followed by performance degradation and device failure. Efficient heat dissipation is becoming an important problem in electronic products. To mitigate this problem, the integration of advanced thermal management materials on electronic devices can significantly improve their heat dissipation capabilities.     Diamond has excellent thermal properties, the highest isotropic thermal conductivity of all bulk materials (k= 2300W/mK), and has an ultra-low coefficient of thermal expansion at room temperature (CTE=1ppm/K). Diamond particle reinforced copper matrix (diamond/copper) composites, as a new generation of thermal management materials, have received great attention due to their potential high k value and adjustable CTE.   However, there are significant mismatches between diamond and copper in many properties, including but not limited to CTE (a clear difference in order of magnitude, as shown in Figure (a)) and chemical affinity (no solid solution, no chemical reaction, as shown in Figure (b)).     Significant performance differences between copper and diamond (a) coefficient of thermal expansion (CTE) and (b) phase diagram Source: Paper   These mismatches inevitably result in low bond strength and high thermal stress at the diamond/copper interface inherent in the high temperature manufacturing or integration process of diamond/copper composites. As a result, diamond/copper composites will inevitably encounter interface cracking problems, and the heat conductivity will be greatly reduced (when diamond and copper are directly combined, its k value is even much lower than pure copper (< 200W/mK)).   At present, the main improvement method is to chemically modify the diamond/diamond interface through metal alloying or surface metallization. The transitional interlayer formed on the interface will improve the interface bonding force, and the relatively thick interlayer is more conducive to withstand the interface cracking. As mentioned in the references, to achieve bonding, the thickness of the interlayer needs to be hundreds of nanometers or even micrometers. However, transitional interlayers on the diamond/copper interface, such as carbides (TiC, ZrC, Cr3C2, etc.), have lower intrinsic thermal conductivity ( 900°C (close to the melting point of copper) and a low sintering pressure of ~ 50MPa. However, in our proposed LTHP process, the sintering temperature is designed to be 600°C, well below the melting point of copper. At the same time, by replacing the traditional graphite mold with a cemented carbide mold, the sintering pressure can be greatly increased to 300MPa. The sintering time of the above two processes is 10 minutes. In the supplementary materials, we have made a supplementary explanation on the optimization of LTHP process parameters. Detailed experimental parameters for different processes (LTHP and HTLP) are shown in Figure (b) above.   Conclusion   The above research aims to overcome these challenges and elucidate the mechanisms for improving the heat transfer performance of diamond/copper composites.   1. A new integrated strategy was developed to combine ultra-thin interface modification with LTHP sintering process. The obtained diamond/copper composite achieves a high k value of 763W/mK and a CTE value of less than 10ppm/K. At the same time, a higher k value can be obtained at a lower diamond volume fraction (45%, compared to 50%-70% in traditional powder metallurgy processes), which means that costs can be significantly reduced by reducing the content of diamond fillers.   2. Through the proposed strategy, the fine interface structure is characterized as a diamond /TiC/CuTi2/Cu layered structure, which greatly reduces the transition interlayer thickness to ~ 100nm, far less than the hundreds of nanometers or even a few microns previously used. However, due to the reduction of thermal stress damage during the preparation process, the interfacial bond strength is still improved to the covalent bond level, and the interfacial bond energy is 3.661J/m2. 3. Due to the ultra-thin thickness, the carefully made diamond/copper interface transition sandwich has low thermal resistance. At the same time, MD and Ab-initio simulation results show that the diamond/titanium carbide interface has good phonon property matching and excellent heat transfer capability (G>800MW/m2K). Therefore, the two possible heat transfer bottlenecks are no longer the limiting factors at the diamond/copper interface.   4. The interface bond strength is effectively improved to the level of covalent bond. However, the interfacial heat transfer capacity (G= 93.5MW/m2K) was not affected, resulting in an excellent balance between the two key factors. The analysis shows that the simultaneous improvement of these two key factors is the reason for the excellent thermal conductivity of diamond/copper composites.    

Clear ultimate Miller RM 56-02 sapphire Crystal Tourbillon watch   Light and transparent are the two major trends of modern technology, and it looks like simple classic design is much better than messy and complicated. Nowadays, it is also the development trend of the watch industry to make watches that meet the public aesthetic and have no shortage of brand style. Light and simple to say, but it is more difficult to do. The weight of the process material itself and the double test of the design have set a barrier for the brand, and the watch pioneer Miller has created this ultra-thin and transparent sapphire crystal tourbillon watch with its cutting-edge watchmaking process and innovative watchmaking design.     The weight of the watch is reduced by the base plate made of sapphire crystal, the RM movement is completely suspended in the sapphire glass case, and is fixed by four steel cables only 0.35mm in size, the device at the 9 point position is used to adjust the tightness of the cable, and the arrow indicator located below the 12 point is used to show whether the entire cable structure is normal to ensure the normal operation of the movement. Every part of the watch is full of the crystallization of artisan wisdom.   The three-layer case of the watch is made of sapphire crystal milling process. A one-of-a-kind, wrist-hugging, ultra-comfortable three-layer case. Sapphire crystal is made of fine alumina crystal powder formed into crystals, it has excellent wear resistance.   The upper and lower bezels of the watch face are treated with anti-glare treatment, using two transparent nitrile rubber O-rings, and assembled with 24 Grade 5 titanium alloy spline screws, waterproof to a depth of 30 meters. Translucent strap, silky soft touch, as if with the skin as one, beautiful and generous, add a beautiful landscape between the wrist.     Inherits the classic craftsmanship tradition of RM, coupled with modern aesthetic and innovative cable fixed watch elements, making the tourbillon watch itself more attractive. Lightweight and transparent is the perfect interpretation of Miller's innovative watchmaking process. Unlike the luxury of other watches, this watch is full of technology and technology, and it is also one of the most attractive watches in the brand's many classic funds. RM 56-02 watch limited launch worldwide, like the watch friends may wish to pay attention to its style.        

What is wafer slicing technology   As a key link in semiconductor manufacturing process, wafer cutting and slicing technology is directly related to chip performance, yield and production cost.   #01 Background and significance of wafer cutting   1.1 Definition of wafer cutting   Wafer cutting (or slicing) is an important part of the semiconductor manufacturing process, the purpose of which is to divide the wafer through multiple processes into multiple independent grains. These grains often contain complete circuit functions and are the core components that are ultimately used to manufacture electronic products. With the reduction of chip design complexity and size, the accuracy and efficiency of wafer cutting technology are increasingly required.     In practice, wafer cutting usually uses high-precision cutting tools such as diamond blades to ensure that each grain remains intact and functional. The preparation before cutting, the precise control in the cutting process and the quality inspection after cutting are the key links. Before cutting, the wafer needs to be marked and positioned to ensure that the cutting path is accurate; In the process of cutting, it is necessary to strictly control the parameters such as the pressure and speed of the tool to prevent damage to the wafer. After cutting, a comprehensive quality inspection is also required to ensure that each chip meets the performance standards.   The basic principle of wafer cutting technology not only includes the selection of cutting equipment and the setting of process parameters, but also involves the mechanical properties of materials and the influence of material characteristics on the cutting quality. For example, low-K dielectric silicon wafers are easily affected by stress concentration during cutting due to their poor mechanical properties, resulting in failure problems such as cracking and cracking. The low hardness and brittleness of low-K materials make them more prone to structural failure when subjected to mechanical forces or thermal stress, especially during cutting, where tool contact with the wafer surface and high temperatures further exacerbate stress concentration.     With the progress of materials science, wafer cutting technology is not only applied to traditional silicon-based semiconductors, but also extended to new semiconductor materials such as gallium nitride. These new materials, due to their hardness and structural properties, bring new challenges to the cutting process and require further improvements in cutting tools and technologies.   Wafer cutting, as a key process in the semiconductor industry, is still being optimized as demand changes and technology advances, laying the foundation for future microelectronics and integrated circuit technology.   In addition to the development of auxiliary materials and tools, the improvement of wafer cutting technology also covers many aspects such as process optimization, equipment performance improvement and precise control of cutting parameters. These improvements are designed to ensure high precision, high efficiency and stability in the wafer cutting process to meet the semiconductor industry's demand for smaller, more integrated and more complex chips.       1.2 Importance of wafer cutting   Wafer cutting plays a key role in the semiconductor manufacturing process, directly affecting subsequent processes as well as the quality and performance of the final product. The following details the importance of wafer cutting from several aspects.   First, cutting accuracy and consistency are key to ensuring chip yield and reliability. In the manufacturing process, the wafer goes through multiple processes to form a number of tiny circuit structures, which need to be precisely divided into independent chips (grains). If the positioning or cutting error in the cutting process is large, it may cause circuit damage, and then affect the function and reliability of the chip. Therefore, high-precision cutting technology can not only ensure the integrity of each chip, but also avoid damage to the internal circuit of the chip and improve the yield.     Second, wafer cutting has a significant impact on production efficiency and cost control. Wafer cutting is an important step in the manufacturing process, and its efficiency directly affects the progress of subsequent processes. By optimizing the cutting process, increasing the degree of automation and cutting speed of the equipment, the overall production efficiency can be significantly improved. On the other hand, the material loss during cutting is also an important part of the cost control of enterprises. The use of advanced cutting technology can not only reduce unnecessary material waste in the cutting process, but also improve the utilization rate of wafers, thereby reducing production costs.   With the advancement of semiconductor technology, the diameter of wafer is increasing, and the circuit density is also increasing, which puts higher requirements on cutting technology. Large wafers require more precise cutting path control, especially in the high-density circuit area, where any small deviation can cause multiple chips to fail. In addition, larger wafers mean more cutting lines and more complex process steps, and cutting technology must further improve its accuracy, consistency, and efficiency to meet these challenges.   1.3 Wafer cutting process   The process flow of wafer cutting covers from the preparation stage to the final quality check, and each step is crucial to ensure the quality and performance of the chip after cutting. The following is a detailed explanation of the various stages.       The wafer cutting process involves cleaning, positioning, cutting, cleaning, inspecting and sorting wafers, and each step is critical. With the advancement of automation, laser cutting, and AI inspection technology, modern wafer cutting systems can achieve higher accuracy, speed, and lower losses. In the future, new cutting technologies such as laser and plasma will gradually replace traditional blade cutting to adapt to more complex chip design needs and further promote the development of semiconductor manufacturing processes.   #02 Wafer cutting technology and its principle   Three common wafer cutting techniques are shown in the figure, namely Blade Dicing, Laser Dicing and Plasma Dicing. The following is a detailed analysis of these three technologies and a supplementary explanation:     Wafer cutting is a key step in the semiconductor manufacturing process, which requires the selection of the appropriate cutting method according to the thickness of the wafer. First, you need to determine the thickness of the wafer. If the thickness of the wafer is more than 100 microns, the blade cutting method can be selected for cutting. If blade cutting is not applicable, you can turn to the fracture cutting method, which includes both scratch cutting and blade cutting.     When the wafer thickness is between 30 and 100 microns, the DBG (Dice Before Grinding) method is recommended. In this case, you can choose to scratch cut, blade cut, or change the cutting order as needed to achieve the best results.   For ultra-thin wafers with a thickness of less than 30 microns, laser cutting becomes the preferred method because it enables precise cutting of thin wafers without causing excessive damage. If laser cutting cannot meet specific requirements, plasma cutting methods can be used as an alternative. This flowchart provides a clear decision path to ensure that the most appropriate wafer cutting technology is selected for different thickness conditions.   2.1 Mechanical cutting technology   Mechanical cutting technology is the traditional method in wafer cutting, its core principle is to use high-speed rotating diamond grinding wheel cutting tool to cut wafer. Key equipment includes aerostatic spindles that drive diamond wheel tools at high speeds for precise cutting or slotting operations along a preset cutting path. This technology is widely used in the industry because of its low cost, high efficiency and wide applicability.     Advantage   The high hardness and wear resistance of diamond grinding wheel tools enable mechanical cutting technology to adapt to the cutting needs of a variety of wafer materials, whether traditional silicon-based materials or new compound semiconductors. Its simple operation and relatively low technical requirements have further promoted its popularity in mass production. In addition, compared with other cutting methods, such as laser cutting, the cost is more controllable, which is suitable for the needs of enterprises in mass production.   Limitation   Although mechanical cutting technology has many advantages, its limitations can not be ignored. First of all, due to the physical contact between the tool and the wafer, its cutting accuracy is relatively limited, and it is easy to produce size deviation, which affects the accuracy of subsequent packaging and testing of the chip. Secondly, the mechanical cutting process is easy to produce cracks, cracks and other defects, which not only affect the yield, but also may have a negative impact on the reliability and service life of the chip. This mechanical stress-induced damage is particularly bad for high-density chip manufacturing, especially when cutting brittle materials.   Technical improvement   To overcome these limitations, researchers continue to optimize the mechanical cutting process. It is an important improvement measure to improve the cutting precision and durability by improving the design and material selection of the grinding wheel tool. In addition, the structural design and control system of the cutting equipment are optimized to further improve the stability and automation level of the cutting process. These improvements reduce the error caused by human operation and improve the consistency of cutting. The introduction of advanced detection and quality control technology, real-time monitoring of abnormal conditions in the cutting process, but also effectively improve the reliability of cutting and yield.   Future development and new technologies   Although mechanical cutting technology still occupies an important position in the wafer cutting field, with the advancement of semiconductor processes, new cutting technologies are also developing rapidly. For example, the application of thermal laser cutting technology provides a new way to solve the problems of precision and defects in mechanical cutting. This non-contact cutting method can reduce the impact of physical stress on the wafer, greatly reducing the incidence of edge breakage and cracks, especially for cutting brittle materials. In the future, the combination of mechanical cutting technology and emerging cutting technologies will provide a wider range of options and flexibility for semiconductor manufacturing, further improving the manufacturing efficiency and quality of chips.   To sum up, mechanical cutting technology, despite its shortcomings, still plays an important role in semiconductor manufacturing through continuous technological improvement and combination with new cutting technologies, and is expected to maintain its competitiveness in future processes.   2.2 Laser cutting technology   Laser cutting technology as a new method in wafer cutting, because of its high precision, no mechanical contact damage and fast cutting characteristics, gradually received wide attention in the semiconductor industry. The technology uses the high energy density and focusing ability of the laser beam to create tiny heat-affected zones on the surface of the wafer material. When the laser beam is applied to the wafer, the thermal stress generated will cause the material to break at a predetermined location, achieving the effect of precise cutting.   Advantages of laser cutting technology   1. High precision: The precise positioning ability of the laser beam can achieve the cutting accuracy of the micron or even the nano level, meeting the requirements of modern high-precision and high-density integrated circuit manufacturing.   2. No mechanical contact: laser cutting does not need to contact the wafer, avoiding the common problems such as edge breakage and cracks during mechanical cutting, and significantly improving the chip yield and reliability.   3. Fast cutting speed: The high speed of laser cutting helps to improve production efficiency, especially for large-scale and high-speed production scenarios.     Challenges faced   1. High equipment cost: the initial investment of laser cutting equipment is high, especially for small and medium-sized production enterprises, and the promotion and application are still facing economic pressure.   2. Complex process control: Laser cutting requires precise control of multiple parameters such as energy density, focus position and cutting speed, and the process is highly complex.   3. Heat affected zone problem: Although the non-contact characteristics of laser cutting reduce mechanical damage, the heat affected zone caused by thermal stress may adversely affect the performance of the wafer material, and further optimization of the process is required to reduce this impact.   Direction of technological improvement   To solve these problems, researchers are focusing on reducing equipment costs, improving cutting efficiency and optimizing process flow.   1. Efficient lasers and optical systems: Through the development of more efficient lasers and advanced optical systems, not only can reduce equipment costs, but also improve cutting accuracy and speed.   2. Optimization of process parameters: In-depth study of laser and wafer material interaction, improve the process to reduce heat affected zone, improve cutting quality.   3. Intelligent control system: Develop intelligent control technology to realize the automation and intelligence of the laser cutting process and improve the stability and consistency of the cutting process.   Laser cutting technology performs particularly well in ultra-thin wafers and high-precision cutting scenarios. With the increase of wafer size and circuit density, traditional mechanical cutting methods are difficult to meet the needs of modern semiconductor manufacturing for high precision and high efficiency, and laser cutting is gradually becoming the first choice in these fields because of its unique advantages.   Although laser cutting technology still faces challenges such as equipment cost and process complexity, its unique advantages in high precision and no contact damage make it an important development direction in the semiconductor manufacturing field. With the continuous progress of laser technology and intelligent control systems, laser cutting is expected to further improve the efficiency and quality of wafer cutting in the future, and promote the sustainable development of the semiconductor industry.   2.3 Plasma cutting technology   As a new wafer cutting method, plasma cutting technology has attracted much attention in recent years. The technology uses high energy ion beam to cut the wafer accurately, and achieves the ideal cutting effect by accurately controlling the energy, speed and cutting path of the ion beam.   Working principle and advantages   The process of plasma cutting wafer relies on the equipment to produce a high-temperature high-energy ion beam, which can heat the wafer material to a melting or gasification state in a very short time, so as to achieve rapid cutting. Compared with traditional mechanical or laser cutting, plasma cutting is faster and has a smaller heat-affected area on the wafer, effectively reducing cracks and damage that may occur during cutting.   In practical applications, plasma cutting technology is particularly good at dealing with complex shapes of wafers. Its high energy plasma beam is flexible and adjustable, which can easily handle irregular shapes of wafers and achieve high precision cutting. Therefore, the technology has shown broad application prospects in the field of microelectronics manufacturing, especially in the high-end chip manufacturing of customized and small-batch production.   Challenges and limitations   Although plasma cutting technology has many advantages, it also faces some challenges. First of all, the process is complex and relies on high-precision equipment and experienced operators to ensure the accuracy and stability of the cutting. In addition, the high temperature and high energy characteristics of isoion beam put forward higher requirements for environmental control and safety protection, increasing the difficulty and cost of application.     Future development direction   Wafer cutting quality is critical to subsequent chip packaging, testing, and the performance and reliability of the final product. The common problems in the cutting process include cracks, edge breakage and cutting deviation, which are influenced by many factors.       The improvement of cutting quality requires comprehensive consideration of many factors such as process parameters, equipment and material selection, process control and detection. Through continuous improvement of cutting technology and optimization of process methods, the precision and stability of wafer cutting can be further improved, and more reliable technical support can be provided for the semiconductor manufacturing industry.   #03 Processing and testing after wafer cutting   3.1 Cleaning and drying   The cleaning and drying process after wafer cutting is essential to ensure chip quality and the smooth progress of subsequent processes. In this process, it is not only necessary to thoroughly remove the silicon chips, coolant residues and other pollutants generated during cutting, but also to ensure that the chip is not damaged during the cleaning process, and to ensure that there is no water residue on the surface of the chip after drying to prevent corrosion or electrostatic discharge caused by water.       The cleaning and drying process after wafer cutting is a complex and delicate process that requires a combination of factors to ensure the final treatment effect. Through scientific methods and rigorous operations, we can ensure that each chip enters the subsequent packaging and testing process in the best state.   3.2 Detection and testing   The chip inspection and testing process after wafer cutting is a key step to ensure product quality and reliability. This process can not only screen out chips that meet the design specifications, but also find and deal with potential problems in a timely manner.       The chip inspection and testing process after wafer cutting covers many aspects such as appearance inspection, size measurement, electrical performance test, functional test, reliability test and compatibility test. These steps are interconnected and complementary, and together constitute a solid barrier to ensure product quality and reliability. Through rigorous inspection and testing processes, potential problems can be identified and dealt with in a timely manner, ensuring that the final product can meet the needs and expectations of customers.   3.3 Packaging and Storage   The wafer-cut chip is a key output in the semiconductor manufacturing process, and its packaging and storage can not be ignored. Proper packaging and storage measures can not only ensure the safety and stability of the chip during transportation and storage, but also provide a strong guarantee for subsequent production, testing and packaging.       The chip packaging and storage after wafer cutting are crucial. Through the selection of appropriate packaging materials and strict control of the storage environment, the safety and stability of the chip during transportation and storage can be ensured. At the same time, regular inspection and evaluation work provides a strong guarantee for the quality and reliability of the chip.   #04 Challenges during wafer scribing   4.1 Microcracks and damage problems   During wafer scribing, microcracks and damage problems are urgent problems to be solved in semiconductor manufacturing. Cutting stress is the main cause of this phenomenon, which causes small cracks and damage on the wafer surface, resulting in increased manufacturing costs and reduced product quality.     As a fragile material, the internal structure of wafers is prone to change when subjected to mechanical, thermal or chemical stress, resulting in micro-cracks. Although these cracks may not be noticeable initially, they can expand and cause more severe damage as the manufacturing process progresses. Especially in the subsequent packaging and testing process, due to temperature changes and further mechanical stress, these micro-cracks may evolve into obvious cracks and even lead to chip failure.       Wafer surface damage can also not be ignored. These injuries can result from improper use of cutting tools, incorrect setting of cutting parameters, or material defects in the wafer itself. Regardless of the cause, these damages can negatively affect the performance and stability of the chip. For example, damage can cause a change in the value of resistance or capacitance in the circuit, affecting the overall performance.   In order to solve these problems, on the one hand, the stress generation in the cutting process is reduced by optimizing the cutting tools and parameters. For example, using a sharper blade and adjusting the cutting speed and depth can reduce the concentration and transfer of stress to a certain extent. On the other hand, researchers are also exploring new cutting technologies, such as laser cutting and plasma cutting, in order to further reduce the damage to the wafer while ensuring the cutting accuracy.   In general, microcracks and damage problems are key challenges to be solved in wafer cutting technology. Only through continuous research and practice, combined with various means such as technological innovation and quality testing, can the quality and market competitiveness of semiconductor products be effectively improved.   4.2 Heat affected areas and their impact on performance   In thermal cutting processes such as laser cutting and plasma cutting, heat affected areas are inevitably generated on the wafer surface due to high temperatures. The size and extent of this area is affected by a number of factors, including cutting speed, power, and the thermal conductivity of the material. The presence of heat-affected regions has a significant impact on the properties of the wafer material, and thus on the performance of the final chip.   Effects of heat affected areas:   1. Crystal structure change: Under the action of high temperature, the atoms in the wafer material may rearrange, resulting in crystal structure distortion. This distortion reduces the mechanical strength and stability of the material, increasing the risk that the chip will fail during use. 2. Electrical performance changes: Under the action of high temperature, the carrier concentration and mobility in the semiconductor material may change, which affects the conductive performance and current transmission efficiency of the chip. These changes can cause chip performance to degrade or even fail to meet design requirements.       Measures to control heat-affected areas:   1. Optimize cutting process parameters: By reducing cutting speed and reducing power, the generation of heat-affected areas can be effectively reduced.   2. The use of advanced cooling technology: liquid nitrogen cooling, microfluidic cooling and other technologies can effectively limit the range of heat-affected areas and reduce the impact on wafer material performance.   3. Material selection: Researchers are exploring new materials, such as carbon nanotubes and graphene, which have excellent heat conduction properties and mechanical strength, and can improve chip performance while reducing heat-affected areas.   In general, heat affected zone is an unavoidable problem in thermal cutting technology, but its influence on wafer material properties can be effectively controlled through reasonable process optimization and material selection. Future research will pay more attention to the refinement and intelligent development of thermal cutting technology to achieve more efficient and accurate wafer cutting.   4.3 Trade-offs between wafer yield and production efficiency   The trade-off between wafer yield and production efficiency is a complex and critical issue in wafer cutting and slicing. These two factors directly affect the economic benefits of semiconductor manufacturers, and are related to the development speed and competitiveness of the entire semiconductor industry.   The improvement of production efficiency is one of the goals pursued by semiconductor manufacturers. As market competition intensifies and the replacement rate of semiconductor products accelerates, manufacturers need to produce a large number of chips quickly and efficiently to meet market demand. Therefore, increasing production efficiency means that wafer processing and chip separation can be completed faster, which reduces production cycles, reduces costs, and increases market share.   Yield challenges: However, the pursuit of high production efficiency often has a negative impact on wafer yield. During wafer cutting, cutting equipment accuracy, operator skills, raw material quality and other factors can lead to wafer defects, damage, or dimensional discrepancies, thereby reducing yield. If the yield is excessively sacrificed in order to improve the production efficiency, it may lead to the production of a large number of unqualified products, causing a waste of resources and damaging the reputation and market position of the manufacturer.     Balance strategy: To find the best balance between wafer yield and production efficiency has become a problem that wafer cutting technology needs to constantly explore and optimize. This requires manufacturers to consider market demand, production cost and product quality and other factors to develop reasonable production strategy and process parameters. At the same time, the introduction of advanced cutting equipment, improve operator skills and strengthen raw material quality control to ensure that production efficiency while maintaining or improving yield.   Future challenges and opportunities: With the development of semiconductor technology, wafer cutting technology is also facing new challenges and opportunities. The continuous reduction of chip size and the improvement of integration put forward higher requirements for cutting accuracy and quality. At the same time, the emergence of emerging technologies provides new ideas for the development of wafer cutting technology. Therefore, manufacturers need to pay close attention to market dynamics and technological development trends, and continue to adjust and optimize production strategies and process parameters to adapt to market changes and technical requirements.   In short, by taking into account market demand, production costs and product quality, and introducing advanced equipment and technology, improving operator skills and strengthening raw material control, manufacturers can achieve the best balance between wafer yield and production efficiency in the wafer cutting process, resulting in efficient and high-quality semiconductor product production.   4.4 Future Outlook   With the rapid development of science and technology, semiconductor technology is advancing at an unprecedented speed, and wafer cutting technology, as a key link, will usher in a new chapter of development. Looking ahead, wafer cutting technology is expected to achieve significant improvements in precision, efficiency and cost, injecting new vitality into the continued development of the semiconductor industry.   Improve accuracy   In the pursuit of higher precision, wafer cutting technology will continue to push the limits of existing processes. Through in-depth study of the physical and chemical mechanisms in the cutting process, as well as precise control of cutting parameters, more fine cutting effects will be achieved in the future to meet the increasingly complex circuit design needs. In addition, the exploration of new materials and cutting methods will also significantly improve the yield and quality.   Increase efficiency   The new wafer cutting equipment will pay more attention to intelligent and automated design. The introduction of advanced control systems and algorithms enables the equipment to automatically adjust cutting parameters to different material and design requirements, resulting in a significant increase in production efficiency. At the same time, innovative means such as multi-slice simultaneous cutting technology and rapid blade replacement technology will become the key to improving efficiency.   Reduce cost   Cost reduction is an important direction of wafer cutting technology development. With the development of new materials and cutting methods, equipment costs and maintenance costs are expected to be effectively controlled. In addition, by optimizing the production process and reducing the scrap rate, waste in the production process can be further reduced, thus achieving an overall cost reduction.   Smart Manufacturing and Internet of Things   The integration of intelligent manufacturing and Internet of Things technology will bring new changes to wafer cutting technology. Through interconnection and data sharing between equipment, every step of the production process can be monitored and optimized in real time. This not only improves production efficiency and product quality, but also provides more accurate market forecasting and decision support for enterprises.   In the future, wafer cutting technology will make significant progress in multiple aspects such as accuracy, efficiency and cost. These advances will promote the continued development of the semiconductor industry and bring more scientific and technological innovation and convenience to human society.   Reference:   ZMKJ has advanced production equipment and technical team, which can customize SiC wafers, sapphire wafers, SOI wafers, silicon substrates and other specifications, thicknesses and shapes according to customers' specific requirements.   Singulation, the Moment When a Wafer is Separated into Multiple Semiconductor Chips - SK hynix Newsroom Detecting Chipping Defects in Wafer Dicing | SOLOMON 3D (solomon-3d.com) Panasonic and Tokyo Seimitsu Start Taking Orders for Their Jointly Developed Laser Patterning Machine for Plasma Dicing｜NEWS | ACCRETECH - TOKYO SEIMITSU Plasma Dicing Process | Others | Solutions | DISCO Corporation Dicing by Laser (Laser Dicing) | DISCO Technology Advancing the Cutting Edge (discousa.com) Basic Processes Using Blade Dicing Saws | Blade Dicing | Solutions | DISCO Corporation Plasma Dicing 101: The Basics | Innovation | KLA 1 new message (yieldwerx.com) Semiconductor Wafer Cleaning - Precision Grinding の ティ · ディ · シー TDC Corporation (mirror-polish.com)